AD9430BSV-210

12-bit, monolithic, sampling analog-to-digital converter, QFP, 3.3 V power supply

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PartNumber:: AD9430BSV-210

Brand:: Analog Devices - ADI | Pack: QFP | D/C: 05+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
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Products Upload time: 2011-08-10

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Part Number:AD9430BSV-210
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Product Summary

The AD9430BSV-210 is a 12-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The AD9430BSV-210 operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The ADC AD9430BSV-210 requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format.

Parametrics

AD9430BSV-210 absolute maximum ratings: (1)AVDD, DRVDD: 4 V; (2)Analog Inputs: –0.5 V to AVDD + 0.5 V; (3)Digital Inputs: –0.5 V to DRVDD + 0.5 V; (4)REFIN Inputs: –0.5 V to AVDD + 0.5 V; (5)Digital Output Current: 20 mA; (6)Operating Temperature: –55℃ to +125℃; (7)Storage Temperature: –65℃ to +150℃; (8)Maximum Junction Temperature: 150℃; (9)Maximum Case Temperature: 150℃; (10)θJA: 25℃/W, 32℃/W.

Features

AD9430BSV-210 features: (1)SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS; (2)ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS); (3)SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS); (4)Excellent linearity: DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical); (5)2 output data options: Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS; Interleaved or parallel data output option; (6)LVDS at 210 MSPS; (7)700 MHz full-power analog bandwidth; (8)On-chip reference and track-and-hold; (9)Power dissipation = 1.3 W typical @ 210 MSPS; (10)1.5 V input voltage range; (11)3.3 V supply operation; (12)Output data format option; (13)Data sync input and data clock output provided; (14)Clock duty cycle stabilizer.