Product Summary

The 29F400TC-90PFTN is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The 29F400TC-90PFTN is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The 29F400TC-90PFTN can also be reprogrammed in standard EPROM programmers. The standard 29F400TC-90PFTN offers access times 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable(CE), write enable (WE), and output enable (OE) controls. It is programmed by executing the program command sequence.

Parametrics

29F400TC-90PFTN absolute maximum ratings: (1)Storage Temperature:–55℃ to +125℃; (2)Ambient Temperature with Power Applied:–40℃ to +85℃; (3)Voltage with respect to Ground All pins except A9, OE, RESET:-2.0 V to +7.0 V; (4)VCC:–2.0 V to +7.0 V; (5)A9, OE, RESET:–2.0 V to +13.5 V.

Features

29F400TC-90PFTN features: (1)Single 5.0 V read, write, and erase:Minimizes system level power requirements; (2)Compatible with JEDEC-standard commands:Uses same software commands as E2PROMs; (3)Compatible with JEDEC-standard world-wide pinouts:48-pin TSOP(Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type), 44-pin SOP (Package suffix: PF); (4)Minimum 100,000 write/erase cycles; (5)High performance:55 ns maximum access time; (6)Sector erase architecture:One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes, Any combination of sectors can be concurrently erased. Also supports full chip erase; (7)Boot Code Sector Architecture:T = Top sector, B = Bottom sector; (8)Embedded EraseTM Algorithms:Automatically pre-programs and erases the chip or any sector; (9)Embedded ProgramTM Algorithms: Automatically writes and verifies data at specified address; (10)Data Polling and Toggle Bit feature for detection of program or erase cycle completion; (11)Ready/Busy output (RY/BY):Hardware method for detection of program or erase cycle completion; (12)Low Vcc write inhibit ≤ 3.2 V; (13)Erase Suspend/Resume:Suspends the erase operation to allow a read in another sector within the same device; (14)Hardware RESET pin:Resets internal state machine to the read mode; (15)Sector protection:Hardware method disables any combination of sectors from write or erase operations; (16)Temporary sector unprotection:Temporary sector unprotection via the RESET pin.

Diagrams